Multiplication, in binary arithmetic, is generally accomplished by successive shift and add operations. The number to be multiplied is known as the multiplicand (MD), while the number by which the MD is multiplied is known as the multiplier (MR). Since, in the binary number system, an individual binary digit (bit, in the vernacular) can assume the value of 0 or 1 only, multiplication of bits is simple and straight forward. As is the case with decimal multiplication, any number, x, multiplied by 1 is equal to itself x; any number, x, multiplied by 0 is 0.
To perform binary multiplication, the MD is multiplied by each bit in the MR. Thus, when the MR bit in question is a 0, the partial product is 0 (represented by a string of 0s as long as the number of bits in the MD). When the MR bit in question is a 1, the partial product is simply the MD. The mechanics of binary multiplication are similar to those of decimal multiplication. As a consequence, binary multiplication is accomplished in a series of multiplicative iterations, one iteration for each bit in the MR, producing a series of partial products for summation. Therefore, binary multiplication is, in its most elemental form, nothing more than the addition of partial products which are either 0 or the MD. Furthermore, each partial product is shifted to the left by the number of bits corresponding to the bit position of the MR bit in question.
A typical computer hardware implementation of a binary multiplier consists of three n-bit registers, an n-bit binary shifting mechanism, and an n-bit adder. The MD and MR are stored, for the duration of the multiplication operation, in two of the registers. The third register stores the result of each iteration of the multiplication procedure, known as the partial product. The partial product, for any given iteration of the multiplication, is equal to the sum of the partial product of the previous iteration and the product of the particular MR bit in question and MD. The sum is formed by the n-bit adder. The product of the MR bit and MD will equal zero if the MR bit equals zero and will equal the MD, shifted left by the number of places equal to the MR bit location, if the MR bit equals one.
Some computer hardware designers employ a "bit-sliced" design to implement a binary multiplier. In a typical "sliced-design," with the slice size equaling the radix of each iteration, several basic binary multipliers (slices) are cascaded. That is, the output from the adder of one multiplier is connected to the partial product register of its neighboring multiplier.
A basic problem with bit-sliced multipliers is that they often take many slice stages (cells) to implement. With emitter coupled logic (ECL) or Gallium Arsenide (GaAs) microchip technology, multipliers are generally implemented in a sliced-design because of the limited number of cells each chip can hold and the limited chip pin count.
In typical prior art bit-sliced multiplier designs, the interchip connection between slices introduce relatively long delays significantly lengthening the time needed to complete a multiplication operation. One particular cause of interchip delay stems from the fact that with each interchip connection, time is consumed in voltage magnitude translations between chips.